1. Field of the Invention
The present invention generally relates to manufacturing methods of electronic devices, and more specifically, to a manufacturing method of an electronic device, the method including a step of removing a resist by ashing after P (phosphorus) ions are implanted.
2. Description of the Related Art
Conventionally and continuously, in a manufacturing process of an electronic device such as a manufacturing process of a semiconductor device or a manufacturing process of a liquid crystal panel or an active substrate of an organic EL panel, an ion implantation method has been used for forming a source/drain region or the like. A photoresist has been used as an ion implantation mask.
After the ion implantation, it is necessary to remove this photoresist mask. Recently, instead of a wet process using removal liquid for removing this photoresist mask, an ashing process using O2 plasma has been used. An example of a related art ashing step is discussed with reference to FIG. 1 and FIG. 2 (See Japanese Laid-Open Patent Application Publication No. 11-097421). Here, FIG. 1 is a first view explaining a related art ashing step. FIG. 2 is a second view explaining a related art ashing step.
Referring to FIG. 1, first, an element isolation region 202 is formed in a p-type silicon substrate 201 so that an element forming region is defined. After that, a phosphorus (P) ion is implanted in a part of the element forming region so that an n-type well region 203 and a boron (B) ion is implanted in another part of the element forming region so that a p-type well region 204 is formed.
Next, after a gate dielectric film 205 is formed by applying a thermal oxidation process, gate electrodes 206 and 207 are formed by forming a polysilicon film on an entire surface and by patterning.
Then, P ions 209 are implanted into the p-type well region 204 in a state where the n-type well region 203 is covered with the resist mask 208, so that an n-type source/drain region 210 is formed.
A deformed layer 211 due to the implantation of the P ion is formed on a surface of the resist mask 208.
Next, cations and electrons are removed from plasma of gas where O2 is the main ingredient and N2, H2, and CF4 are added so that a neutral radical environment 212 is made. In the neutral radical environment 212, an ashing process is applied and thereby the deformed layer 211 and the resist mask 208 are removed.
In a case where the ashing process is implemented at a high temperature so that processing speed is made high, in order to prevent a phenomenon where non-deformed resist pops, a step for removing the deformed layer 211 is implemented at 150° C. of substrate temperature. After the deformed layer 211 is removed, the non-deformed resist mask 208 is removed at 200° C. of the substrate temperature.
Referring to FIG. 2, after the processed substrate is taken out to the atmosphere, a cleaning process using a sulfuric acid water solution is applied to the processed substrate so that ashing residual is removed. After that, B ions are implanted into the n-type well region 203 in a state where the p-type well region 204 is covered with the resist mask 213, and thereby a p-type source/drain region 215 is formed.
Next, cations and electrons are removed from plasma of gas where O2 is the main ingredient and N2, H2, and CF4 are added so that neutral radical environment 217 is made. In the neutral radical environment 217, an ashing process is applied and thereby a deformed layer 216 and the resist mask 213 are removed. As a result of this, a basic part of a CMOS transistor is formed.
In this case, in order to prevent the popping phenomenon, a step for removing the deformed layer 216 is implemented at 150° C. substrate temperature. After the deformed layer 216 is removed, non-deformed resist mask 213 is removed at 200° C. substrate temperature.
On the other hand, a technique where, in order to implement the ashing process at a constant substrate temperature, the ashing process is applied to the deformed layer in O2 plasma including 1% of CF4 and at 180° C. substrate temperature so that the deformed layer is removed, and then the ashing process is applied to a non-deformed resist mask in O2 plasma including 5% N2.
As accompanying making the speed of the semiconductor device high, in order to achieve an increase of the driving electric current and the reduction of a leakage current, implantation of impurities is repeated a considerable number of times. It is necessary to remove the resist used as the ion implantation mask. Hence, as the number of implantations is increased, the number of removals of the resist is increased. This causes an increase of the manufacturing time.
Accordingly, currently, as discussed above, the substrate temperature at the time of removing the resist is equal to or higher than 150° C., and thereby reaction speed is made high and the resist removal time is reduced.
Furthermore, in the ashing device having a load lock room, in a case where a semiconductor wafer processed at high temperature is taken out to the atmosphere via the load lock room, temperature unevenness is generated between a part contacting with a substrate supporting jig such as an arm and a non-contacting part. As a result of this, heat deformation may be generated when the semiconductor wafer is rapidly cooled in the atmosphere so that the semiconductor wafer may be warped. Alternatively, thermal stress may be generated so that breakage or short-circuiting of wiring may occur.
Japanese Laid-Open Patent Application Publication No. 11-345771 discloses a technique where a cooling mechanism is provided at the load lock room, a processed semiconductor wafer is mounted on a wafer mounting stage provided at the load lock room so that uniform heat distribution is maintained, and the temperature of the semiconductor wafer is decreased to a designated temperature.
Japanese Laid-Open Patent Application Publication No. 2001-319885 discloses a technique where the processed wafer is self-cooled by opening the load lock room when the pressure of the load lock room becomes atmospheric pressure or by leading inactive gas into the load lock room when the pressure of the load lock room is changed to atmospheric temperature.
However, the inventor of the present invention found that a Si digging phenomenon occurs in the ashing step after P having a high density of 5×1015 cm−2 is ion-implanted. The Si digging phenomenon is a phenomenon where a P implantation region or a polysilicon layer where P is implanted of the silicon substrate is undesirably etched.
FIG. 3 is a cross-sectional view of a main part after a contact hole is formed. More specifically, FIG. 3 is a sketch of an electron micrograph image and a cross-sectional view in a direction parallel with an extending direction of a gate electrode.
FIG. 3-(A) shows a normal state and FIG. 3-(B) shows an abnormal state. Referring to FIG. 3-(B), a hollow part 226 is formed at a corner of a contact hole 224 of a silicon substrate 221 where P is implanted. Furthermore, a hollow part 227 is formed in a region neighboring the contact hole 224.
Since the hollow part 227 in the region neighboring to the contact hole 224 is generated before the contact hole 224 is formed, a step before the contact hole 224 with the hollow part 226 is formed, namely the ashing step after the P ion implantation region is formed, may be the reason for this situation.
FIG. 4 is a cross-sectional view of a state where a resist used as a mask is removed by ashing after the polysilicon layer for the gate electrode is formed and the P ions are partially implanted in order to form an n channel type FET gate electrode and a gate extraction electrode. FIG. 4 is a sketch of an electron micrograph image.
Referring to FIG. 4, the film thickness of a P implantation part of a polysilicon layer is thinner than a non-implantation part situated at the left end side of FIG. 4. This shows that undesirable etching is generated.
Such a Si digging defect causes an increase on the value of resistance of a diffusion resistance layer or a wiring layer so that a signal delay or decrease of the driving electrical current may happen.
In a case where B ions are implanted as shown in FIG. 5-(A), as compared to the P ion implantation shown in FIG. 5-(B), the Si digging defect shown in FIG. 5-(C) does not occur at all. This situation is applied to a case of another impurity such as As and it is confirmed that this situation is peculiar to P.
FIG. 6 is a view for explaining distribution of the Si digging defects.
FIG. 6-(A) shows a distribution indicated by dots without the Si digging defect, in a case where the wafer is taken to the atmosphere after a long time such as approximately 30 through 60 seconds has passed after the ashing process. The distribution is almost even in the wafer.
FIG. 6-(B) shows distribution showing the Si digging defect in a case where the wafer is taken to the atmosphere after a short time such as approximately 10 seconds passes after the ashing process, by dots. The defect in the case of FIG. 6-(B) is larger than the case of FIG. 6-(A) by the Si digging defects.
Thus, if the time period from the time of the ashing process to the time when the wafer is taken out to the atmosphere is long, the temperature of the wafer is decreased so that it may be difficult to generate the Si digging defects.